Plating copper through-holes or vias is a requirement for double-sided and multilayer circuits. In a previous column we discussed the plating process; specifically copper seed coating using electroless copper and Shadow plating, which is then followed with an electroplating process. There are a number of variations on how this plating process can be sequenced with the imaging and etching processes to create slightly different plating profiles. It is typical in the printed circuit industry to refer to these options as:

Panel plating deposits copper on the entire panel. As a consequence, in addition to plating the vias, panel plating builds up metal on the entire surface on both sides of the substrate. Panel plating is usually performed before any imaging step. For a double-sided circuit, once the sheet is panel-plated, it can be coated with photoresist then imaged and etched using conventional circuit fabrication techniques. An advantage of panel plating is variation issues from current density are minimized (since it is a uniformly plated sheet of laminate). One disadvantage is copper is added everywhere and a significant amount will end up getting etched away after imaging. This consumes additional plating resources. Another disadvantage is the circuits become less flexible and susceptible to fracture as electrodeposited copper is added to the top of the rolled annealed copper. Third, panel plating adds variation to the copper thickness which is a negative effect if circuits are used in controlled impedance applications.

Pattern plating only deposits copper on selected areas, as an imaged resist coating is used to define the pattern. The first step, after imaging and developing the photoresist pattern, is to plate the “pattern” of exposed copper, then follow with a tin plating that will act as an etch resist. After etching, the photoresist is stripped away (chemically removed), leaving a pattern of tin plating on copper. The tin acts as an etch resist when the unwanted background copper is etched away. The tin is then stripped off leaving just the plated-up copper traces. It consumes less plating resources than a typical panel plate, and creates the circuit pattern with just one imaging operation. The disadvantage is that there is still added copper on the remaining traces. Again, this could be an issue for flexibility or impedance control.  

With bussed plating, the copper trace pattern is first created using a typical print and etch process.  Then the patterned traces are plated up (including the vias). An apparent advantage of this technique is that only one imaging operation is needed. However the disadvantages are substantial, including:

1) The entire pattern of traces must be physically connected to insure electroplating throughout. Any breaks in the electrical connection will result in non-plated surfaces.

2) The traces will likely create situations of uneven current density and distribution, which can affect plating thickness consistency.

3) As in the pattern plating process, copper is plated on all the traces and this may cause issues with flexibility and impedance control.

4) Fine line traces limit the current carrying capability and can cause difficulty in plating. Bussed plating of copper traces was far more common in the “old days” of circuit fabrication where trace width requirements did not dramatically affect plating current densities. Today, bussed plating is most often used to electroplate gold (hard or soft) on select surfaces requiring keypad buttons, multiple connector insertions, or gold ball wire bonding.

Pads only plating is a variation of pattern plating as an image resist covers the entire panel except the pads that capture the vias. So only the vias and small pads get electroplated. After via plating the resist is stripped off and followed with an additional resist/image operation that defines the circuit traces connecting the pads.  Unwanted copper areas are then etched away. The advantage of this method is that it avoids flexibility issues or impedance issues from the added copper on the traces. It tends to be slightly more costly since two imaging operations are needed to define the traces. In the world of flexible circuits many applications require either dynamic flexing or impedance control, so pads only plating is often the best choice. Another synonymous term for this process sequence is “button plating.”

While many circuit fabrication shops do all of the above variations, it is more difficult to attain best efficiency and process control with many plating sequence variations. Most facilities attempt to standardize on one or two options. Unfortunately the mixture of product requirements makes standardization impossible. Pads only plating gives the best options for circuit fabricators that are building fine line circuits with dynamic flex needs or high speed electronic applications requiring impedance control. Pattern plating is a good option when impedance or dynamic flexing is not a requirement as this is a less costly method to plate the vias. And bussed designs are often required to selectively plate precious metals.

The following are step-by-step pictorials of how the pads only process vs. the pattern plating process works.

Below depicts a typical double-sided laminate. The laminate consists of two copper films bonded on each side of a dielectric film.

The next step is to form via openings, which is usually done with a mechanical drill.

In order to electroplate vias, a “seed” coating or metallic layer needs to be coated over the entire via opening to enable a subsequent electroplating process. The chemical coating needs to adhere to both dielectric and copper so the entire surface is coated. This seed coating is usually electroless copper or direct plating using a carbon- or graphite-based process. In the case of Shadow plating (graphite), only the conductive material attached to the dielectric remains on the final circuit.

After seed coating, a photoresist is coated and imaged on the panel. The resist is a negative image of the desired conductor pattern. The areas exposed by the developed resist will get electroplated. The image below shows the resist exposing the pad area surrounding the via and a trace space.

Copper is electroplated over the entire surface except the areas covered with resist.

The next step is to electroplate “sacrificial” tin that will be used as the etch resist.

After tin plating the resist is stripped and the copper is etched. The tin plating acts as an etch resist.

The next step is to strip the tin. The result is the final circuit pattern.

The primary drawback with the pattern plating method is copper is plated on all traces and remains after processing is completed. This added plated layer of copper can cause flexibility/flex life issues as well as negatively impact impedance control, which requires a very homogenous metal layer of precise thickness.

For applications that require dynamic flexing or impedance control, the best method is a “pads only” plating process which metallizes the vias but leaves the traces free of plated copper.

Plating copper through-holes or vias is a requirement for double-sided and multilayer circuits. In a previous column we discussed the plating process; specifically copper seed coating using electroless copper and Shadow plating, which is then followed with an electroplating process. There are a number of variations on how this plating process can be sequenced with the imaging and etching processes to create slightly different plating profiles. It is typical in the printed circuit industry to refer to these options as:

Panel plating deposits copper on the entire panel. As a consequence, in addition to plating the vias, panel plating builds up metal on the entire surface on both sides of the substrate. Panel plating is usually performed before any imaging step. For a double-sided circuit, once the sheet is panel-plated, it can be coated with photoresist then imaged and etched using conventional circuit fabrication techniques. An advantage of panel plating is variation issues from current density are minimized (since it is a uniformly plated sheet of laminate). One disadvantage is copper is added everywhere and a significant amount will end up getting etched away after imaging. This consumes additional plating resources. Another disadvantage is the circuits become less flexible and susceptible to fracture as electrodeposited copper is added to the top of the rolled annealed copper. Third, panel plating adds variation to the copper thickness which is a negative effect if circuits are used in controlled impedance applications.

Pattern plating only deposits copper on selected areas, as an imaged resist coating is used to define the pattern. The first step, after imaging and developing the photoresist pattern, is to plate the “pattern” of exposed copper, then follow with a tin plating that will act as an etch resist. After etching, the photoresist is stripped away (chemically removed), leaving a pattern of tin plating on copper. The tin acts as an etch resist when the unwanted background copper is etched away. The tin is then stripped off leaving just the plated-up copper traces. It consumes less plating resources than a typical panel plate, and creates the circuit pattern with just one imaging operation. The disadvantage is that there is still added copper on the remaining traces. Again, this could be an issue for flexibility or impedance control.  

With bussed plating, the copper trace pattern is first created using a typical print and etch process.  Then the patterned traces are plated up (including the vias). An apparent advantage of this technique is that only one imaging operation is needed. However the disadvantages are substantial, including:

1) The entire pattern of traces must be physically connected to insure electroplating throughout. Any breaks in the electrical connection will result in non-plated surfaces.

2) The traces will likely create situations of uneven current density and distribution, which can affect plating thickness consistency.

3) As in the pattern plating process, copper is plated on all the traces and this may cause issues with flexibility and impedance control.

4) Fine line traces limit the current carrying capability and can cause difficulty in plating. Bussed plating of copper traces was far more common in the “old days” of circuit fabrication where trace width requirements did not dramatically affect plating current densities. Today, bussed plating is most often used to electroplate gold (hard or soft) on select surfaces requiring keypad buttons, multiple connector insertions, or gold ball wire bonding.

Pads only plating is a variation of pattern plating as an image resist covers the entire panel except the pads that capture the vias. So only the vias and small pads get electroplated. After via plating the resist is stripped off and followed with an additional resist/image operation that defines the circuit traces connecting the pads.  Unwanted copper areas are then etched away. The advantage of this method is that it avoids flexibility issues or impedance issues from the added copper on the traces. It tends to be slightly more costly since two imaging operations are needed to define the traces. In the world of flexible circuits many applications require either dynamic flexing or impedance control, so pads only plating is often the best choice. Another synonymous term for this process sequence is “button plating.”

While many circuit fabrication shops do all of the above variations, it is more difficult to attain best efficiency and process control with many plating sequence variations. Most facilities attempt to standardize on one or two options. Unfortunately the mixture of product requirements makes standardization impossible. Pads only plating gives the best options for circuit fabricators that are building fine line circuits with dynamic flex needs or high speed electronic applications requiring impedance control. Pattern plating is a good option when impedance or dynamic flexing is not a requirement as this is a less costly method to plate the vias. And bussed designs are often required to selectively plate precious metals.

The following are step-by-step pictorials of how the pads only process vs. the pattern plating process works.

Below depicts a typical double-sided laminate. The laminate consists of two copper films bonded on each side of a dielectric film.

The next step is to form via openings, which is usually done with a mechanical drill.

In order to electroplate vias, a “seed” coating or metallic layer needs to be coated over the entire via opening to enable a subsequent electroplating process. The chemical coating needs to adhere to both dielectric and copper so the entire surface is coated. This seed coating is usually electroless copper or direct plating using a carbon- or graphite-based process. In the case of Shadow plating (graphite), only the conductive material attached to the dielectric remains on the final circuit.

After seed coating, a photoresist is coated and imaged on the panel. The resist is a negative image of the desired conductor pattern. The areas exposed by the developed resist will get electroplated. The image below shows the resist exposing the pad area surrounding the via and a trace space.

Copper is electroplated over the entire surface except the areas covered with resist.

The next step is to electroplate “sacrificial” tin that will be used as the etch resist.

After tin plating the resist is stripped and the copper is etched. The tin plating acts as an etch resist.

The next step is to strip the tin. The result is the final circuit pattern.

The primary drawback with the pattern plating method is copper is plated on all traces and remains after processing is completed. This added plated layer of copper can cause flexibility/flex life issues as well as negatively impact impedance control, which requires a very homogenous metal layer of precise thickness.

For applications that require dynamic flexing or impedance control, the best method is a “pads only” plating process which metallizes the vias but leaves the traces free of plated copper.

The first steps of via formation and seed plating are the same as pattern plating.

After the seed coating, photoresist is imaged so it exposes only the pads that capture the via.

Copper is electroplated in the vias and pad areas as shown below.

The resist is stripped and the panel goes through a second image resist operation.

The panel then goes through an etch-strip operation—the image below shows the copper etched away. The resist is “tented” over the via to protect the through-holes from etchant.

The image below shows the resist stripped away leaving the final circuit pattern.

Plating, imaging and etching are basic operations used in flexible circuit and PCB fabrication. The sequence and combination of these operations can result in significantly different circuit configurations. Changing the order of processes can result in different plating thickness profiles. These operations are also dependent on each other for attaining desired yields. The interactions among various process steps, and achieving desired plating results, is understandably complex. We highly recommend involvement of a supplier for technical questions about specific applications.

Dave Becker is the V.P. of sales and marketing at All Flex Flexible Circuits and Heaters. To contact Becker, or read past columns, click here.

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